Dynamic Random Access Memory (DRAM) structures capable of achieving high threshold voltage with minimal threshold implants are needed to minimize leakage and to obtain high chip yield. In today's semiconductor industry, with high-scale integration plus increased device complexities, isolation features are needed to allow for a maximum number of device features to be incorporated within a given area of a substrate. As such, isolation features such as shallow trench isolation structures are commonly added to integrated circuit devices such as DRAMs. The main source of leakage for storage trench DRAMs is buried strap leakage stemming from the array threshold ion implant. This implant is needed to provide sufficient threshold voltage to prevent sub-threshold leakage in the array. These leakages are tied to the physical structure of the device through the transistor at the steps, or corners of the main device formed where the main device adjoins the shallow trench isolation features.
Shallow trench isolation structures typically include a step, or corner at the intersection between the semiconductor substrate and the shallow trench isolation filler material, which typically extends above the semiconductor substrate. At the location where the polysilicon film, which forms the gates of transistors, extends over this step, an electric field is created. When a divot is formed at the intersection of the shallow trench isolation device and the semiconductor substrate, this electric field is enhanced. The divot produces an enhanced electric field at the corner of the gate, which lowers the threshold voltage, Vt, at the corner of the surface channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices, for example, an N-type MOSFET in the DRAM. This necessitates additional Vt implant which produces additional buried strap leakage. As the divot size increases, the required implant and associated leakage increases. The undesired formation of divots at the edges of shallow trench isolation devices is a common problem.
The conventional way to minimize divot formation and size is to anneal the oxide that is used to fill the shallow trench isolation. Annealing the oxide lowers the etch rate in aqueous hydrofluoric acid (HF), thereby minimizing the HF attack which creates the divots. The anneal can oxidize silicon in the deep and shallow trench, however, and produce defects that can destroy the device. Nitride liners in the shallow trench improve this condition, but create other defects. Even when such a nitride liner is present, annealing the shallow trench can contribute to other problems such as variable retention time problems.
The presence of the nitride liner along the sidewall of the trench may result in parasitic edge (sidewall) conduction in buried channel MOSFETs, such as the p-type Field Effect Transistors (p-FET's) used in contemporary DRAMs. This parasitic edge conduction is caused by electrons which become trapped at the nitride-oxide interface as a result of high-energy etching processes and, also, due to hot-carrier injection during normal operation. Thus, the nitride liner degrades performance of p-FETs as these hot carriers are injected into the edge area of nitride liner by the p-FET corner. Also, the nitride liner is recessed by pad nitride removal. The recess deepens the divot leading to problems such as reduced Vt and polysilicon stringers which short adjacent gates.
There is another disadvantage associated with annealing the oxide used to fill the shallow trench isolation (STI) device. Annealing is a costly and time-consuming step. The added cost of annealing is multiplied for some processes, for example, whereby a second oxide deposition is added to the STI after a first fill/anneal process sequence. The second oxide must also be annealed in a second annealing process if the device will be subsequently exposed to aqueous hydrofluoric acid (HF) because the aqueous HF will etch the un-annealed oxide at a higher rate than the annealed oxide, thus creating voids. If a second annealing operation is performed to anneal the new oxide film, the total annealing cost is doubled.
Another approach to minimizing the reduction in Vt due to leakage, is to form a spacer adjacent the shallow trench isolation film which extends above the substrate surface, so that the polysilicon gate does not extend over a sharp corner. This concept was discussed in U.S. Pat. No. 5,521,422, issued to Mandelman et al. If such a structure is to be produced by the current processing known in the art, then, a pad nitride pullback process step must be carried out first to provide a region adjacent to the STI structure over which the spacer can be formed. It must be sufficient to ensure that there is still STI filler material in the corner formed at the intersection of the STI structure and the substrate, after the initial (pad) oxide film is subsequently removed. If the STI used in this approach has a nitride liner, then the strip processes may additionally create a lateral void formed by the recession of nitride liner away from the corner. These voids or divots must be filled to avoid polysilicon shorts. The repeated use of nitride to re-fill the nitride liner recess leads to the p-FET problems discussed above. This pulled-back nitride STI structure is particularly difficult to form as the minimum lithography shrinks in size since the pad nitride film gets "pulled-back" to accommodate the spacers which are formed adjacent to the STI, and at the expense of active device area.
What is needed is a shallow trench process which does not produce an exposed nitride liner and which reduces parasitic corner conduction in surface channel MOSFETs by providing structures and processes which minimize divot formation. What is needed is a device wherein no portion of the nitride liner is present in the region of the sidewall which is prone to parasitic conduction in buried-channel p-FETs.
Furthermore, there is a need for a structure where the edge of the gate is displaced laterally away from the corner of the shallow trench isolation device, and which can be combined with a storage capacitor, especially one using a buried strap, to produce low leakage transistors due to the absence of any exposed nitride liners. There is also a particular need to produce low power merged logic-DRAM chips that have low leakage in both the array and the p-FET's.
In current nitride lined STI processes, a Catch-22 has been created. A large divot eliminates the leakage problems associated with trapped charge where the gate of a transistor steps over a corner exposing a nitride liner in the p-FET, but increases leakage in the array through the extra array dopant that is required to turn off the transistor because of the enhanced electric field created by the divot at the corner. As such, a shallow trench isolation device, which has corners which are substantially divot-free and do not include the nitride liner, is especially desirable.